Download Advanced ASIC chip synthesis: using Synopsys Design by Himanshu Bhatnagar PDF

By Himanshu Bhatnagar

Complex ASIC Chip Synthesis: utilizing Synopsys TM layout CompilerTM actual CompilerTM and PrimeTime TM, moment variation describes the complicated innovations and strategies used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. furthermore, the complete ASIC layout movement method specific for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.

The emphasis of this ebook is on real-time software of Synopsys instruments, used to wrestle numerous difficulties noticeable at VDSM geometries. Readers may be uncovered to a good layout technique for dealing with complicated, sub-micron ASIC designs. importance is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to structure, actual synthesis, and static timing research. At every one step, difficulties with regards to each one part of the layout stream are pointed out, with suggestions and work-around defined intimately. furthermore, the most important matters relating to structure, such as clock tree synthesis and back-end integration (links to structure) also are mentioned at size. moreover, the ebook comprises in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding types, designated in the direction of optimum synthesis answer. objective audiences for this publication are practising ASIC layout engineers and masters point scholars venture complicated VLSI classes on ASIC chip layout and DFT concepts.

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Additional resources for Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime

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However, if the design is failing hold-time requirements, you may either fix these violations at the pre-layout level, or may postpone this step until after layout. Many designers prefer the latter approach for minor hold-time violations (also used here), since the pre-layout synthesis and timing analysis uses the statistical wire-load models and fixing the hold-time violations at the pre-layout level may result in setup-time violations for the same path, after layout. It must be noted that gross hold-time violations should be fixed at the pre-layout level, in order to minimize the number of hold-time fixes, which may result after the layout.

In this instance if we were to use the dynamic simulation method to verify the gate-level, it would have taken a long time (days and weeks, depending on the size of the design) to verify the design. In comparison, the formal method would take a few hours to perform a similar verification. The last part involves verifying the gate-level netlist against the gate-level netlist. This too is a significant step for the verification process, since it is mainly used to verify – what has gone into the layout versus what has come out of the layout.

11. Back-annotate the real extracted data to PrimeTime. 12. Post-layout static timing analysis using PrimeTime. 13. Functional gate-level simulation of the design with post-layout timing (if desired). 14. Tape out after LVS and DRC verification. 1 Chapter 1 Physical Synthesis Traditionally synthesis methods are based on using the wire-load models. The basic nature of the wire-load models is such that they are fanout based. In other words, the delay computation of cells is performed based on the number of fanouts a cell drives.

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